SDRAM is another of those powerful acronyms that describes a lot more than it sounds like it does. The letters stand for Synchronous Dynamic Random Access Memory, and it is a fast method of delivering computing capacity. SDRAM can run at 133 Mhz, which is much faster than earlier RAM technologies.
SDRAM is very protective of its data bits, storing them each in a separate capacitor. The benefit of this is the avoidance of corruption and the maintenance of "pristine" data. The drawback is that those same capacitors that are so useful at storing the SDRAM bits also happen to be very bad at keeping electrons in check; the result is where the Dynamic part of the name comes in, as refreshes are required to maintain data integrity. Once all of that dynamic refreshing and storing are done with, the result is a dense package of data, one of the densest in the business world.
It add the Synchronous part with a subroutine that lines itself up with the computer system bus and processor, so that all operations take place at the same time. Specifically, the computer's internal clock drives the entire mechanism. Once the clock sends out a signal saying that another unit of time has passed, the SDRAM chips go to work. In addition to the dense data package of DRAM, SDRAM allows a more complex memory pattern, giving you an extremely powerful method of storing and accessing data.
Another benefit of SDRAM is what is called pipelining. Because the SDRAM chips are so dense and complex, they can accept more than one write command at a time. This means that a chip can be processing one command while it accepts another one, even if that new command has to wait its turn in the pipeline. Previous RAM chips required proprietary access, allowing only one command at a time throughout the chip. In this way, SDRAM chips are faster than their predecessors.
This mostly describes single-data SDRAM chips, or SDR SDRAM. An even newer kind of chip is double-data-rate SDRAM, or DDR SDRAM. This allows for even greater bandwidth by making pipeline data transfers twice for every unit of time put forth by the computer's internal clock. One transfer takes place at the beginning of the new unit of time; the other takes place at the end.
SDRAM chips first came to the computing forefront in 1997. In just three years, they had become the dominant force in memory chips across the computing spectrum.
SDRAM is very protective of its data bits, storing them each in a separate capacitor. The benefit of this is the avoidance of corruption and the maintenance of "pristine" data. The drawback is that those same capacitors that are so useful at storing the SDRAM bits also happen to be very bad at keeping electrons in check; the result is where the Dynamic part of the name comes in, as refreshes are required to maintain data integrity. Once all of that dynamic refreshing and storing are done with, the result is a dense package of data, one of the densest in the business world.
It add the Synchronous part with a subroutine that lines itself up with the computer system bus and processor, so that all operations take place at the same time. Specifically, the computer's internal clock drives the entire mechanism. Once the clock sends out a signal saying that another unit of time has passed, the SDRAM chips go to work. In addition to the dense data package of DRAM, SDRAM allows a more complex memory pattern, giving you an extremely powerful method of storing and accessing data.
Another benefit of SDRAM is what is called pipelining. Because the SDRAM chips are so dense and complex, they can accept more than one write command at a time. This means that a chip can be processing one command while it accepts another one, even if that new command has to wait its turn in the pipeline. Previous RAM chips required proprietary access, allowing only one command at a time throughout the chip. In this way, SDRAM chips are faster than their predecessors.
This mostly describes single-data SDRAM chips, or SDR SDRAM. An even newer kind of chip is double-data-rate SDRAM, or DDR SDRAM. This allows for even greater bandwidth by making pipeline data transfers twice for every unit of time put forth by the computer's internal clock. One transfer takes place at the beginning of the new unit of time; the other takes place at the end.
SDRAM chips first came to the computing forefront in 1997. In just three years, they had become the dominant force in memory chips across the computing spectrum.
SDRAM control signals
All commands are timed relative to the rising edge of a clock signal. In addition to the clock, there are 6 control signals, mostly active, which are sampled on the rising edge of the clock:
CKE Clock Enable. When this signal is low, the chip behaves as if the clock has stopped. No commands are interpreted and command latency times do not elapse. The state of other control lines is not relevant. The effect of this signal is actually delayed by one clock cycle. That is, the current clock cycle proceeds as usual, but the following clock cycle is ignored, except for testing the CKE input again. Normal operations resume on the rising edge of the clock after the one where CKE is sampled high.Put another way, all other chip operations are timed relative to the rising edge of a masked clock. The masked clock is the logical AND of the input clock and the state of the CKE signal during the previous rising edge of the input clock.
/CS Chip Select. When this signal is high, the chip ignores all other inputs (except for CKE), and acts as if a NOP command is received.
DQM Data Mask. (The letter Q appears because, following digital logic conventions, the data lines are known as "DQ" lines.) When high, these signals suppress data I/O. When accompanying write data, the data is not actually written to the DRAM. When asserted high two cycles before a read cycle, the read data is not output from the chip. There is one DQM line per 8 bits on a x16 memory chip or DIMM.
/RAS Row Address Strobe. Despite the name, this is not a strobe, but rather simply a command bit. Along with /CAS and /WE, this selects one of 8 commands.
/CAS Column Address Strobe. Despite the name, this is not a strobe, but rather simply a command bit. Along with /RAS and /WE, this selects one of 8 commands.
/WE Write enable. Along with /RAS and /CAS, this selects one of 8 commands. This generally distinguishes read-like commands from write-like commands.
SDRAM devices are internally divided into 2 or 4 independent internal data banks. One or two bank address inputs (BA0 and BA1) select which bank a command is directed toward.
Many commands also use an address presented on the address input pins. Some commands, which either do not use an address, or present a column address, also use A10 to select variants.
The commands understood are as follows.
All commands are timed relative to the rising edge of a clock signal. In addition to the clock, there are 6 control signals, mostly active, which are sampled on the rising edge of the clock:
CKE Clock Enable. When this signal is low, the chip behaves as if the clock has stopped. No commands are interpreted and command latency times do not elapse. The state of other control lines is not relevant. The effect of this signal is actually delayed by one clock cycle. That is, the current clock cycle proceeds as usual, but the following clock cycle is ignored, except for testing the CKE input again. Normal operations resume on the rising edge of the clock after the one where CKE is sampled high.Put another way, all other chip operations are timed relative to the rising edge of a masked clock. The masked clock is the logical AND of the input clock and the state of the CKE signal during the previous rising edge of the input clock.
/CS Chip Select. When this signal is high, the chip ignores all other inputs (except for CKE), and acts as if a NOP command is received.
DQM Data Mask. (The letter Q appears because, following digital logic conventions, the data lines are known as "DQ" lines.) When high, these signals suppress data I/O. When accompanying write data, the data is not actually written to the DRAM. When asserted high two cycles before a read cycle, the read data is not output from the chip. There is one DQM line per 8 bits on a x16 memory chip or DIMM.
/RAS Row Address Strobe. Despite the name, this is not a strobe, but rather simply a command bit. Along with /CAS and /WE, this selects one of 8 commands.
/CAS Column Address Strobe. Despite the name, this is not a strobe, but rather simply a command bit. Along with /RAS and /WE, this selects one of 8 commands.
/WE Write enable. Along with /RAS and /CAS, this selects one of 8 commands. This generally distinguishes read-like commands from write-like commands.
SDRAM devices are internally divided into 2 or 4 independent internal data banks. One or two bank address inputs (BA0 and BA1) select which bank a command is directed toward.
Many commands also use an address presented on the address input pins. Some commands, which either do not use an address, or present a column address, also use A10 to select variants.
The commands understood are as follows.
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